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evaluation kit available _______________________________________________________________ maxim integrated products 1 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maxim-ic.com. ultra-low-power, octal, 12-bit, 50msps, 1.8v adc with serial lvds outputs MAX19527 19-5309; rev 0; 6/10 general description the MAX19527 is an octal, 12-bit analog-to-digital converter (adc), optimized for the low-power and high-dynamic performance requirements of medical imaging instrumentation and digital communications applications. the device operates from a single 1.8v supply and consumes 440mw (55mw per channel), while providing a 69dbfs signal-to-noise ratio (snr) at a 5.3mhz input frequency. in addition to low operating power, the device features programmable power man - agement for idle states and reduced-channel operation. an internal 1.25v precision bandgap reference sets the full-scale range of the adc to 1.5v p-p . a flexible refer - ence structure allows the use of an external reference for applications requiring greater gain accuracy or a different input voltage range. a programmable common- mode voltage reference output is provided to enable dc-coupled input applications. various adjustments and feature selections are avail - able through programmable registers that are accessed through the 3-wire serial peripheral interface (spi k ). a flexible clock input circuit allows for a single-ended, logic-level clock or a differential clock signal. an on-chip pll generates the multiplied (6x) clock required for the serial lvds digital outputs. the serial lvds output provides programmable test patterns for data timing alignment and output drivers with programmable current drive and programmable internal termination. the device is available in a small, 10mm x 10mm x 1.2mm, 144-lead thin chip ball grid array (ctbga) pack - age and is specified for the extended industrial (-40 n c to +85 n c) temperature range. applications ultrasound and medical imaging instrumentation multichannel communications zif gsm and td-scdma transceivers features s ultra-low-power operation 55mw per channel at 50msps s single 1.8v power supply s excellent dynamic performance 69dbfs snr at 5.3mhz 140dbc/hz near-carrier snr at 1khz offset from a 5.3mhz tone 84dbc sfdr at 5.3mhz 90db channel isolation at 5.3mhz s user-programmable adjustment and feature selection through an spi interface s serial lvds outputs with programmable current drive and internal termination s programmable power management s internal or external reference operation s single-ended or differential clock input s programmable output data format s built-in output data test patterns s small, 10mm x 10mm, 144-lead ctbga package s evaluation kit available (order MAX19527evkit+) ordering information spi is a trademark of motorola, inc. + denotes a lead(pb)-free/rohs-compliant package. part temp range pin-package MAX19527exe+ -40 n c to +85 n c 144 ctbga
ultra-low-power, octal, 12-bit, 50msps, 1.8v adc with serial lvds outputs MAX19527 2 stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. avdd, ovdd to gnd ......................................... -0.3v to +2.1v ognd to gnd ...................................................... -0.3v to +0.3v in_+, in_-, cmout, refio, refh, refl, clkin+, clkin- to gnd .............. -0.3v to the lower of (v avdd + 0.3v) and +2.1v out_+, out_-, frame+, frame-, clkout+, clkout-, shdn, cs , sclk, sdio to gnd ............. -0.3v to the lower of (v ovdd + 0.3v) and +2.1v continuous power dissipation (t a = +70 n c) 144-lead ctbga (derate 37mw/ n c above +70 n c) multilayer board ...................................................... 2963mw operating temperature range ......................... -40 n c to +85 n c junction temperature .................................................... +150 n c storage temperature range .......................... -65 n c to +150 n c lead temperature (soldering, 10s) ................................ +300 n c soldering temperature (reflow) ...................................... +260 n c electrical characteristics (v avdd = 1.8v, v ovdd = 1.8v, internal reference, a in = -0.5dbfs, differential clock, v clkd = 1.5v p-p , f clk = 50mhz, programmable registers at default settings (table 1), t a = -40 n c to +85 n c, typical values are at t a = +25 n c, unless otherwise noted.) (note 1) absolute maximum ratings parameter symbol conditions min typ max units dc accuracy resolution 12 bits integral nonlinearity inl f in = 5.3mhz q 0.5 q 1.7 lsb differential nonlinearity dnl f in = 5.3mhz, no missing codes q 0.3 q 1.0 lsb offset error oe internal reference q 0.07 q 0.7 %fs gain error ge external reference = 1.25v q 0.2 q 3.0 %fs analog inputs (in_+, in_-) (figure 2) input differential range v diff in_+ - in_- 1.5 v p-p common-mode input voltage range v cm q 50mv tolerance 1050 mv input resistance r in fixed resistance to gnd > 100 k i differential input resistance, common mode connected to inputs 4 input current i in switched capacitance input current, each input, v cm = 1.050v 36 f a input capacitance c ins fixed capacitance to gnd, each input 1 pf c ind fixed differential capacitance 0.2 c sample switched capacitance, each input 1.5 conversion rate maximum clock frequency f clk 50 mhz minimum clock frequency f clk 25 mhz data latency figure 5 8.5 clock cycles
ultra-low-power, octal, 12-bit, 50msps, 1.8v adc with serial lvds outputs MAX19527 3 electrical characteristics (continued) (v avdd = 1.8v, v ovdd = 1.8v, internal reference, a in = -0.5dbfs, differential clock, v clkd = 1.5v p-p , f clk = 50mhz, programmable registers at default settings (table 1), t a = -40 n c to +85 n c, typical values are at t a = +25 n c, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units dynamic performance small-signal noise floor ssnf analog input < -35dbfs, f in = 5.3mhz -69.5 dbfs near-carrier signal-to-noise ratio ncsnr 1khz offset from 5.3mhz full-scale tone, c refio = c refh/refl = 0.1 f f (figure 3) 140 dbc/hz 8-channel coherent sum 147 signal-to-noise ratio snr f in = 5.3mhz at -0.5dbfs 67.0 68.5 db f in = 19.3mhz at -0.5dbfs 68.5 signal-to-noise and distortion ratio sinad f in = 5.3mhz at -0.5dbfs 66.6 68.2 db f in = 19.3mhz at -0.5dbfs 68.2 spurious-free dynamic range sfdr f in = 5.3mhz at -0.5dbfs 70.0 84 dbc f in = 19.3mhz at -0.5dbfs 84 total harmonic distortion thd f in = 5.3mhz at -0.5dbfs -81 -72 dbc f in = 19.3mhz at -0.5dbfs -81 intermodulation distortion imd f in1 = 5.15mhz at -6.5dbfs, f in2 = 5.45mhz at -6.5dbfs -83 db full-power bandwidth fpbw r source = 50 i differential > 500 mhz overdrive recovery time 6db beyond full scale (recover accuracy to < 1% of full scale) < 1 clock cycles interchannel characteristics crosstalk f in = 5.3mhz at -0.5dbfs -90 db gain matching f in = 5.3mhz q 0.1 db phase matching f in = 5.3mhz q 0.25 degrees analog output (cmout) cmout output voltage v cmout default programming state 1.05 1.10 1.15 v internal reference refio output voltage v refio bypass only, no dc load 1.22 1.25 1.28 v refio temperature coefficient tc ref < q 60 ppm/ n c refh voltage v refh bypass only, no dc load 1.61 v refl voltage v refl bypass only, no dc load 0.86 v external reference refio input voltage range v refin +5%/-15% tolerance 1.25 v refio input resistance r refin 10 q 20% k i
ultra-low-power, octal, 12-bit, 50msps, 1.8v adc with serial lvds outputs MAX19527 4 electrical characteristics (continued) (v avdd = 1.8v, v ovdd = 1.8v, internal reference, a in = -0.5dbfs, differential clock, v clkd = 1.5v p-p , f clk = 50mhz, programmable registers at default settings (table 1), t a = -40 n c to +85 n c, typical values are at t a = +25 n c, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units clock inputs (clkin+, clkin-)differential mode (figure 4) differential clock input voltage v clkd 0.4 to 2.0 v p-p common-mode voltage v clkcm self-biased 1.2 v dc-coupled clock signal 1.0 to 1.4 input resistance r clk differential, default setting 10 k i differential, programmable internal termination selected 0.1 common mode to gnd 9 input capacitance c clk capacitance to gnd, each input 3 pf clock inputs (clkin+, clkin-)single-ended mode (clkin- < 0.1v) (figure 4) single-ended mode selection threshold (clkin-) v il 0.1 v single-ended clock input high threshold (clkin+) v ih 1.5 v single-ended clock input low threshold (clkin+) v il 0.3 v input leakage (clkin+) i ih v ih = 1.8v +5 f a i il v ih = 0v -5 input leakage (clkin-) i il v ih = 0v -150 -50 f a input capacitance (clkin+) 3 pf digital inputs (shdn, sclk, sdin, cs ) input high threshold v ih 1.5 v input low threshold v il 0.3 v input leakage i ih v ih = 1.8v +5 f a i il v il = 0v -5 input capacitance c din 3 pf digital outputs (sdio) output voltage low v ol i sink = 200 f a 0.2 v output voltage high v oh i source = 200 f a ovdd - 0.2 v lvds digital outputs (out_+/out_-, clkout+/clkout-, frame+/frame-) differential output voltage |v od | external r load = 100 i 250 450 mv output offset voltage v os external r load = 100 i 1.125 1.375 v power-management characteristics (figure 3) wake-up time from sleep mode t swake internal reference, c refio = 0.1 f f, c refh/refl = 0.1 f f; q 1% gain error, with respect to steady-state gain 10 ms wake-up time from nap mode t nwake internal reference, c refio = 0.1 f f, c refh/refl = 0.1 f f; q 1% gain error, with respect to steady-state gain 2 f s
ultra-low-power, octal, 12-bit, 50msps, 1.8v adc with serial lvds outputs MAX19527 5 electrical characteristics (continued) (v avdd = 1.8v, v ovdd = 1.8v, internal reference, a in = -0.5dbfs, differential clock, v clkd = 1.5v p-p , f clk = 50mhz, programmable registers at default settings (table 1), t a = -40 n c to +85 n c, typical values are at t a = +25 n c, unless otherwise noted.) (note 1) note 1: specifications are 100% production tested at t a r +25 n c. specifications for t a < +25 n c are guaranteed by design and characterization. note 2: specifications guaranteed by design and characterization. parameter symbol conditions min typ max units serial peripheral interface (spi) timing (figure 9, note 2) sclk period t sclk 50 ns sclk to cs setup time t css 10 ns sclk to cs hold time t csh 10 ns sdio to sclk setup time t sds serial-data write 10 ns sdio to sclk hold time t sdh serial-data write 0 ns sclk to sdio output data delay t sdd serial-data read 10 ns timing characteristics (figures 6 and 7, note 2) data valid to clkout rise/fall t od t sample / 24 - 0.10 t sample / 24 + 0.05 t sample / 24 + 0.20 ns clkout output-width high t ch t sample /12 ns clkout output-width low t cl t sample /12 ns frame rise to clkout rise t df t sample / 24 - 0.10 t sample / 24 + 0.05 t sample / 24 + 0.20 ns sample clk rise to frame rise t sf t sample / 2 + 1.6 t sample / 2 + 2.3 t sample / 2 + 3.3 ns power requirements analog supply voltage v avdd 1.7 1.8 1.9 v digital output supply voltage v ovdd 1.7 1.8 1.9 v analog supply current i avdd 8 channels active 158 180 ma incremental channel power-down -18 nap mode 13 15 sleep mode 0.35 0.5 digital output supply current i ovdd 8 channels active, external r load = 100 i 87 ma incremental channel power-down -7.4 nap mode 28 sleep mode < 0.1 total power dissipation p td 8 channels active 440 mw incremental channel power-down -46 nap mode 74 sleep mode 0.8
ultra-low-power, octal, 12-bit, 50msps, 1.8v adc with serial lvds outputs MAX19527 6 typical operating characteristics (v avdd = 1.8v, v ovdd = 1.8v, internal reference, a in = -0.5dbfs, differential clock, v clkd = 1.5v p-p , f clk = 50mhz, programmable registers at default settings (table 1), t a = -40 n c to +85 n c, typical values are at t a = +25 n c, unless otherwise noted. specifications are 100% production tested at t a r +25 n c. specifications for t a < +25 n c are guaranteed by design and characterization. ) 5.3mhz input fft plot MAX19527 toc01 frequency (mhz) amplitude (dbfs) 20 15 10 5 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -110 0 25 f in = 5.301324mhz a in = -0.49dbfs snr = 68.58db sinad = 68.35db thd = -81.19dbc sfdr = 85.17db differential nonlinearity vs. digital output code MAX19527 toc07 digital output code dnl (lsb) 3584 3072 2048 2560 1024 1536 512 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 4096 19.3mhz input fft plot MAX19527 toc02 frequency (mhz) amplitude (dbfs) 20 15 10 5 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -110 0 25 f in = 19.303900mhz a in = -0.51dbfs snr = 68.49db sinad = 68.24db thd = -80.90dbc sfdr = 85.73db dynamic performance vs. input frequency max195027 toc08 input frequency (mhz) dynamic performance (db) 150 100 50 65 70 75 80 85 90 60 0 200 sfdr -thd snr sinad crosstalk fft plot MAX19527 toc03 frequency (mhz) amplitude (dbfs) 20 15 10 5 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -110 0 25 measured on channel 1, with interfering signal on channel 2 f in(in1) = 5.301324mhz f in(in2) = 19.303900mhz a in(in1) = -0.5dbfs a in(in2) = -0.5dbfs crosstalk = -92db f in(in2) = 19.3039mhz dynamic performance vs. analog input power MAX19527 toc09 analog input power (dbfs) dynamic performance (db) -5 -10 -45 -40 -35 -25 -20 -30 -15 20 30 40 50 60 70 80 90 10 -50 0 sfdr -thd snr sinad two-tone intermodulation distortion MAX19527 toc04 frequency (mhz) amplitude (dbfs) 20 15 10 5 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -110 0 25 f in1 = 5.154828mhz f in2 = 5.423404mhz a in1 = -6.95dbfs a in2 = -7.02dbfs im3 = -83dbc 5.3mhz input fft plot 8-channel coherent sum MAX19527 toc05 frequency (mhz) amplitude (dbfs) 20 15 10 5 0 0 25 f in = 5.301324mhz a in = -0.50dbfs snr = 77.20db sinad = 76.84db thd = -87.80dbc sfdr = 89.31db -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 -120 integral nonlinearity vs. digital output code MAX19527 toc06 digital output code inl (lsb) 3584 3072 2048 2560 1024 1536 512 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 4096
ultra-low-power, octal, 12-bit, 50msps, 1.8v adc with serial lvds outputs MAX19527 7 typical operating characteristics (continued) (v avdd = 1.8v, v ovdd = 1.8v, internal reference, a in = -0.5dbfs, differential clock, v clkd = 1.5v p-p , f clk = 50mhz, programmable registers at default settings (table 1), t a = -40 n c to +85 n c, typical values are at t a = +25 n c, unless otherwise noted. specifications are 100% production tested at t a r +25 n c. specifications for t a < +25 n c are guaranteed by design and characterization. ) dynamic performance vs. sampling rate MAX19527 toc10 sampling rate (mhz) dynamic performance (db) 45 40 35 30 65 70 75 80 85 90 60 25 50 sfdr snr -thd sinad dynamic performance vs. clock duty cycle MAX19527 toc13 clock duty cycle (%) 65 60 55 50 45 40 35 30 70 dynamic performance (db) 65 70 75 80 85 90 60 sfdr snr -thd sinad single-ended clock mode +6db overdrive output code vs. signal phase signal phase (degrees) +6db overdrive output code 240 300 180 60 120 512 1024 1536 2048 3072 2560 3584 4096 0 0 360 MAX19527 toc16 clipped at 4095 clipped at 0 f in = 5.3mhz a in = +6dbfs dynamic performance vs. input common-mode voltage MAX19527 toc11 input common-mode voltage (v) 1.10 1.05 1.00 0.95 1.15 dynamic performance (db) 65 70 75 80 85 90 60 sfdr snr -thd sinad dynamic performance vs. temperature MAX19527 toc14 temperature (c) dynamic performance (db) 60 35 10 -15 65 70 75 80 85 90 60 -40 85 sfdr snr -thd sinad +6db overdrive error vs. signal phase signal phase (degrees) +6db overdrive error (lsb) 240 300 180 60 120 -0.75 -0.50 -0.25 0 0.50 0.25 0.75 1.00 -1.00 0 360 MAX19527 toc17 f in = 5.3mhz a in = +6dbfs clipped at 4095 clipped at 0 dynamic performance vs. analog supply voltage MAX19527 toc12 v avdd (v) 1.90 1.85 1.80 1.75 1.70 1.65 1.95 dynamic performance (db) 65 70 75 80 85 90 60 sfdr snr -thd sinad near-carrier noise spectrum vs. frequency offset MAX19527 toc15 frequency offset (khz) near-carrier noise spectrum (dbc/ hz) 3 1 -1 -3 -150 -140 -130 -120 -160 -5 5 single channel 8-channel coherent sum analog supply current vs. sampling rate (avdd) MAX19527 toc18 sampling rate (mhz) analog supply current (ma) 45 40 35 30 20 40 60 80 100 120 140 160 180 8 channels 7 channels 4 channels nap mode 0 25 50 1 channel
ultra-low-power, octal, 12-bit, 50msps, 1.8v adc with serial lvds outputs MAX19527 8 typical operating characteristics (continued) (v avdd = 1.8v, v ovdd = 1.8v, internal reference, a in = -0.5dbfs, differential clock, v clkd = 1.5v p-p , f clk = 50mhz, programmable registers at default settings (table 1), t a = -40 n c to +85 n c, typical values are at t a = +25 n c, unless otherwise noted. specifications are 100% production tested at t a r +25 n c. specifications for t a < +25 n c are guaranteed by design and characterization. ) analog supply current vs. temperature (avdd) MAX19527 toc19 temperature (c) analog supply current (ma) 60 35 -15 10 145 150 155 160 170 165 175 180 140 -40 85 analog supply current vs. supply voltage (avdd) MAX19527 toc20 supply voltage (v) analog supply current (ma) 1.90 1.85 1.80 1.75 1.70 145 150 155 160 165 170 140 1.65 1.95 digital supply current vs. sampling rate (ovdd) MAX19527 toc21 sampling rate (mhz) digital supply current (ma) 45 40 35 30 10 20 30 40 50 60 70 80 90 100 0 25 50 8 channels 7 channels 4 channels 1 channel nap mode digital supply current vs. temperature (ovdd) MAX19527 toc22 temperature (c) digital supply current (ma) 60 35 10 -15 80 85 90 95 75 -40 85 digital supply current vs. supply voltage (ovdd) MAX19527 toc23 supply voltage (v) digital supply current (ma) 1.90 1.85 1.80 1.75 1.70 75 80 85 90 95 100 70 1.65 1.95 reference voltage vs. temperature MAX19527 toc24 temperature (c) reference voltage (v) 60 35 10 -15 1.240 1.245 1.250 1.255 1.260 1.230 -40 85 cmout voltage vs. temperature MAX19527 toc25 temperature (c) cmout voltage (v) 60 40 20 0 -20 1.02 1.04 1.06 1.08 1.10 1.12 1.14 1.16 1.18 1.00 -40 80 cmi_adj[2:0] 111 110 101 100 011 010 001 000 cmout voltage vs. cmout load current MAX19527 toc26 cmout load current (a) cmout voltage (v) 800 600 400 200 1.08 1.09 1.10 1.11 1.12 1.07 0 1000 analog input current vs. input common-mode voltage (avdd) MAX19527 toc27 input common-mode voltage (v) analog input current (a) 1.10 1.05 1.00 25 30 35 40 45 50 20 0.95 1.15
ultra-low-power, octal, 12-bit, 50msps, 1.8v adc with serial lvds outputs MAX19527 9 pin description pin configuration pin name function analog inputs c1 in1- channel 1 negative (inverting) analog input c2 in1+ channel 1 positive (noninverting) analog input d1 in2- channel 2 negative (inverting) analog input d2 in2+ channel 2 positive (noninverting) analog input e1 in3- channel 3 negative (inverting) analog input e2 in3+ channel 3 positive (noninverting) analog input f1 in4- channel 4 negative (inverting) analog input f2 in4+ channel 4 positive (noninverting) analog input top view refl n.c. n.c. n.c. ogn d n.c. n.c. n.c. refh refi o o vd d avd d a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 shdn n.c. n.c. n.c. n.c. n.c. n.c. out1 + avdd i.c. out1- n.c. b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 in1- gn d gn d g nd in1+ gnd gnd gnd gnd ognd out2+ out2- c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 gnd ognd out3+ out3- in2- gnd gnd gnd gnd gnd gnd in2+ d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 e1 e2 e3 e4 e5 e6 e7 e8 e9 e10 e11 e12 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 g1 g2 g3 g4 g5 g6 g7 g8 g9 g10 g11 g12 h1 h2 h3 h4 h5 h6 h7 h8 h9 h10 h11 h12 j1 j2 j3 j4 j5 j6 j7 j8 j9 j10 j11 j12 k1 k2 k3 k4 k5 k6 k7 k8 k9 k10 k11 k12 sdio n.c. n.c. n.c. out8 + n.c. n.c. n.c. gn d o ut8- avdd clkin+ l1 l2 l3 l4 l5 l6 l7 l8 l9 l10 l11 l12 m1 m2 m3 m4 m5 m6 m7 m8 m9 m10 m11 m12 gnd ognd out4+ out4- in3- gnd gnd gnd gnd gnd gnd in3+ gnd ovdd clkout+ clkout - in4- cmout gnd gnd gnd avdd gnd in4+ gnd ovdd frame+ frame- in5- cmout gnd gnd gnd avdd gnd in5+ gnd ognd out5+ out5- in6- gnd gnd gnd gnd gnd gnd in6+ gnd ognd out6+ out6- in7- gnd gnd gnd gnd gnd gnd in7+ gnd ognd out7+ out7- in8- gnd gnd gnd gnd gnd gnd in8+ sclk n.c. n.c. n.c. cs n.c. n.c. n.c. gnd ovdd avdd clkin-
ultra-low-power, octal, 12-bit, 50msps, 1.8v adc with serial lvds outputs MAX19527 10 pin description (continued) pin name function g1 in5- channel 5 negative (inverting) analog input g2 in5+ channel 5 positive (noninverting) analog input h1 in6- channel 6 negative (inverting) analog input h2 in6+ channel 6 positive (noninverting) analog input j1 in7- channel 7 negative (inverting) analog input j2 in7+ channel 7 positive (noninverting) analog input k1 in8- channel 8 negative (inverting) analog input k2 in8+ channel 8 positive (noninverting) analog input l8 clkin+ clock positive (noninverting) input m8 clkin- clock negative (inverting) input. if clkin- is connected to ground, clkin+ is a single-ended, logic-level clock input. otherwise, clkin+ and clkin- are self-biased differential clock inputs. lvds outputs b11 out1+ channel 1 positive (noninverting) lvds digital output b12 out1- channel 1 negative (inverting) lvds digital output c11 out2+ channel 2 positive (noninverting) lvds digital output c12 out2- channel 2 negative (inverting) lvds digital output d11 out3+ channel 3 positive (noninverting) lvds digital output d12 out3- channel 3 negative (inverting) lvds digital output e11 out4+ channel 4 positive (noninverting) lvds digital output e12 out4- channel 4 negative (inverting) lvds digital output f11 clkout+ positive (noninverting) serial lvds clock output f12 clkout- negative (inverting) serial lvds clock output g11 frame+ positive (noninverting) frame-alignment lvds output. a rising edge on the differential frame output aligns to a valid output data frame. g12 frame- negative (inverting) frame-alignment lvds output. a rising edge on the differential frame output aligns to a valid output data frame. h11 out5+ channel 5 positive (noninverting) lvds digital output h12 out5- channel 5 negative (inverting) lvds digital output j11 out6+ channel 6 positive (noninverting) lvds digital output j12 out6- channel 6 negative (inverting) lvds digital output k11 out7+ channel 7 positive (noninverting) lvds digital output k12 out7- channel 7 negative (inverting) lvds digital output l11 out8+ channel 8 positive (noninverting) lvds digital output l12 out8- channel 8 negative (inverting) lvds digital output 3-wire serial peripheral interface (spi) l10 sdio spi data input/output m10 sclk spi clock m11 cs spi chip select
ultra-low-power, octal, 12-bit, 50msps, 1.8v adc with serial lvds outputs MAX19527 11 pin description (continued) pin name function reference a8 refh high reference bypass. bypass refh with a 0.1 f f capacitor to refl. see the reference configurations section for details. a9 refio reference input/output. to use internal reference, bypass to gnd with a capacitor value of 0.1 f f. see the reference configurations section for an external reference. a10 refl low reference bypass. bypass refl with a 0.1 f f capacitor to refh. see the reference configurations section for details. supply and bias a7, b8, f7, g7, l7, m7 avdd analog supply voltage. apply 1.8v to all avdd inputs. bypass each input to gnd with a 0.1 f f capacitor. a11, c10, d10, e10, h10, j10, k10 ognd digital ground. connect all gnd (analog ground) and ognd (digital ground) pins to the board ground plane. a12, f10, g10, m12 ovdd digital supply voltage. digital and output driver supply input. apply 1.8v to all ovdd inputs. bypass each input to gnd with a 0.1 f f capacitor. b10 shdn active-high power-down. programmable power-management state selection. see the power management section for details. c3Cc9, d3C d9, e3Ce9, f4, f5, f6, f8, f9, g4, g5, g6, g8, g9, h3Ch9, j3Cj9, k3C k9, l9, m9 gnd analog ground. connect all gnd (analog ground) and ognd (digital ground) pins to the board ground plane. f3, g3 cmout common-mode output. input common-mode reference output. bypass cmout with a 1 f f capacitor to gnd. other a1Ca6, b1C b7, l1Cl6, m1Cm6 n.c. no connection. not internally connected. b9 i.c. internal connection. leave i.c. unconnected.
ultra-low-power, octal, 12-bit, 50msps, 1.8v adc with serial lvds outputs MAX19527 12 simplified block diagram reference and bias generatio n spi, registers, and contro l refio cmout in1+ in1- 12-bit adc refh refl cs sclk sdio shdn digital serializer out1+ out1- lvds in2+ in2- 12-bit adc digital serializer out2+ out2- lvds in8+ in8- 12-bit adc digital 6x 1x serializer out8+ out8- lvds clkin+ clkin- clock circuitry pll clkout+ clkout- lvds frame+ frame- lvds avdd ovdd gnd MAX19527
ultra-low-power, octal, 12-bit, 50msps, 1.8v adc with serial lvds outputs MAX19527 13 detailed description the MAX19527 is an octal, 12-bit, 50msps analog- to-digital converter (adc). the adc features fully differential inputs, a differential, pipelined architecture with digital error correction, 3-wire spi-compatible inter - face for device configuration, serial lvds digital outputs, and fully configurable power management. the device has an internal precision bandgap reference, but the reference structure also allows the use of an external reference. a flexible clock input circuit allows for a single-ended or differential clock signal, while an on-chip configurable pll generates the multiplied (6x) clock required for the serial lvds digital outputs. the adc offers eight separate, fully differential channels with synchronized inputs and outputs. the device features a 9-stage, fully differential, pipelined architecture that is ideal for high-speed conversion while minimizing power consumption (figure 1). sampled signals taken at a channel input move progressively through the pipeline stages every half clock cycle. from input to serial out - put, the total latency is 8.5 clock cycles. each pipeline stage converts its input voltage to a digital output code. at every stage, except the last, the error between the input voltage and the digital output code is multiplied and passed on to the next pipeline stage. digital error correction compensates for adc comparator offsets in each pipeline stage and ensures that there are no missing codes. see the simplified block diagram . analog inputs and common-mode reference apply the differential analog input signal to the analog inputs (in_+, in_-), which are connected to the input sampling switch (figure 2). when the input sampling switch is closed, the input signal is applied to the sampling capacitors through the input switch resistance. the input signal is sampled at the instant the input switch opens. carefully balance the input impedance of in_+ and in_- for optimum performance. before the input switch is closed to begin the next sampling cycle, the sampling capacitors are reset to the input common-mode potential. common-mode bias can be provided externally (default) or internally through 2k i resistors (programmed). in dc-coupled applications, the signal source provides the external bias and the bias current. in ac-coupled applications, the input current is supplied by the common-mode input voltage. for example, the input current can be supplied through the center tap of a transformers secondary winding. figure 1. pipeline architecturestage blocks in1_+ stage 1 in1_- flash adc dac c x2 12 stage 2 stage 8 stage 9, end of pipeline digital error correctio n data[11:0] MAX19527
ultra-low-power, octal, 12-bit, 50msps, 1.8v adc with serial lvds outputs MAX19527 14 alternatively, program the input common-mode control register (04h, see tables 17 and 18 for configuration details) through the spi interface to supply the input dc common-mode voltage and current through inter - nal 2k i resistors (figure 2). when the input current is supplied through the internal resistors, the input common- mode potential is reduced by the voltage drop across the resistors. the common-mode input reference voltage can be adjusted through programmable register settings from 1.020v to 1.160v in 0.020v increments. the default setting is 1.100v. cmout can be used to provide a common- mode output reference to a dc-coupled driving circuit. reference configurations a trimmed internal bandgap voltage generator provides an internal reference voltage of 1.25v. the bandgap volt - age is buffered and applied to refio through a 10k i resistor. the buffered bandgap voltage is applied to a scaling and level-shift circuit, which creates the internal reference potentials (refh, refl) that establish the full-scale range of the adc. a simplified schematic of the reference circuit is shown in figure 3. alternatively, refio can be driven externally for greater gain accuracy, or to establish a different full-scale range. figure 2. internal track-and-hold (t/h) circuit figure 3. simplified reference schematic in_+ cmout in_- 2ki 2ki to other adc channels v co m * avdd c par 1.0pf c sample 1.5pf c sample 1.5pf r switch 100i r switch 100i avdd c par 1.0pf sampling clock *v co m programmable from 1.02v to 1.16v? see the input common-mode and clkin control register (04h ) MAX19527 1.250v 10ki 10ki 10ki bandgap referenc e buffer scale and level shift 0.1f external bypass 0.1f external bypass refio refh refl internal gain?bypass refi o external gain control?drive refi o internal reference (controls adc gain) to pipeline adcs
ultra-low-power, octal, 12-bit, 50msps, 1.8v adc with serial lvds outputs MAX19527 15 internal reference mode in a typical application, the internal absolute gain accuracy is sufficient and the internal reference is used to establish the full-scale range of the adc. an external 0.1 f f bypass capacitor from refio to gnd is recommended. an external bypass capacitor placed across refh and refl is required to achieve optimal near-carrier noise performance, and a value of 0.1 f f is recommended to achieve the performance specified in the electrical characteristics table. when using sleep mode for power management, the wake-up time is determined by the reference-bypass capacitor values. the wake-up from sleep-mode characteristic appears as adc gain vs. time where the adc full-scale voltage is to first order a 2-pole response. the first pole is established by the rc time constant on pin refio. the second pole is established by the rc time constant on pins refh and refl. when the recommended capacitor values are used, the wake-up from sleep time is 10ms. when nap mode is used for power management, the reference remains powered on and the wake-up time from nap mode is not affected by the reference bypass capacitance values. external reference mode in applications where control over the full-scale range of the adc is desired, an external voltage of 1.25v can be applied to refio. for optimal performance, the recommended adjustment range is limited to +5/-15%. the refio-to-adc gain-transfer function is: v fs = 1.5 x [v refio /1.25] as in the case of internal reference mode, apply a 0.1 f f capacitor across pins refh and refl to achieve optimal near-carrier noise performance and provide noise filtering of the external reference source. clock input the input clock interface provides for flexibility in the requirements of the clock driver. the device accepts a fully differential clock or single-ended logic-level clock. the device is specified for an input sampling frequency range of 25mhz to 50mhz. by default, the internal pll is configured to accept input clock frequencies from 39mhz to 50mhz. the pll is programmed through the pll sampling rate register (00h, table 2). table 3 details the complete range of pll sampling frequency settings. for differential clock operation, connect a differential clock to the clkin+ and clkin- inputs. the input common mode is established internally to allow for ac-coupling. the self-biased input common-mode voltage defaults to 1.2v. the differential clock signal can also be dc-coupled if the externally established common-mode voltage is constrained to the specified clock input common-mode range of 1.0v to 1.4v. a differential input termination of 100 i can be switched in by programming the clkin control register (04h[4], table 17). for single-ended operation, connect clkin- to gnd and drive the clkin+ input with a logic-level signal. when the clkin- input is grounded (or pulled below the threshold of the clock-mode detection comparator), the differential-to-single-ended conversion stage is disabled and the logic-level inverter path is activated. the input common-mode self-bias is disconnected from clkin+, and provides a weak pullup bias to avdd for clkin- during single-ended clock operation (figure 4). system timing requirements figure 5 shows the relationship between the analog inputs, input clock, frame-alignment output, serial-clock output, and serial-data outputs. the differential analog input (in_+, in_-) is sampled on the rising edge of the applied clock signal (clkin+, clkin-) and the result - ing data appears at the digital outputs 8.5 clock cycles later. figure 6 provides a detailed, two-conversion timing diagram of the relationship between inputs and outputs. clock output (clkout+, clkout-) the adc provides a differential clock output that con - sists of clkout+ and clkout-. as shown in figure 6, the serial output data is clocked out of the device on both edges of the clock output. the frequency of the output clock is six times (6x) the frequency of the input clock. the output data format and test pattern register (01h) allows the phase of the clock output to be adjusted relative to the output data frame (table 5, figure 10). frame-alignment output (frame+, frame-) the adc provides a differential frame-alignment signal that consists of frame+ and frame-. as shown in figure 6, the rising edge of the frame-alignment signal corresponds to the first bit (d0) of the 12-bit serial-data stream. the frequency of the frame-alignment signal is identical to the frequency of the input clock; however, the duty cycle varies depending on the input clock frequency.
ultra-low-power, octal, 12-bit, 50msps, 1.8v adc with serial lvds outputs MAX19527 16 figure 4. simplified clock input schematic figure 5. global timing diagram clkin+ select threshold avdd 10ki 20ki 5ki 5ki 50i 50i clkin- input common-mode self-bias block clkin_internal 10 0i termination, programmed: 04h[4] differential-to-single-ende d clock conversion single-ended clock mode: inverter path select 2:1 mux differential mode: clkin- > select threshol d single-ended mode: clkin- < select threshold t sample n+1 n+8 n n+2 n+3 n+4 n+5 n+6 n+7 n+9 n+10 n+11 8.5 clock-cycle data latenc y output data for sample n-8 output data for sample n (v in_+ - v in_- ) (v clkin+ - v clkin- ) (v frame+ - v frame- ) (v clkout + - v clkout - ) (v out_ + - v out_- )
ultra-low-power, octal, 12-bit, 50msps, 1.8v adc with serial lvds outputs MAX19527 17 serial output data (out_+, out_-) the adc provides conversion results through individual differential outputs consisting of out_+ and out_-. the results are valid 8.5 input clock cycles after a sample is taken. as shown in figure 5, the output data is clocked out on both edges of the output clock, lsb (d0) first (by default). figure 7 displays the detailed serial-output timing diagram. differential lvds digital outputs the adc features programmable, fully differential lvds digital outputs. by default, the 12-bit data output is transmitted lsb first, in offset binary format. the output data format and test pattern register (01h, table 5) allows customization of the output bit order and data format. the output bit order can be reconfigured to transmit msb first, and the output data format can be changed to twos complement. table 6 contains full output data configuration details. the lvds outputs feature flexible programming options. first, the output common-mode voltage can be programmed from 0.6v to 1.2v (default) in 200mv steps (table 13). use the lvds output driver level register (02h, table 9) to adjust the output common-mode voltage. the lvds output driver current is also fully programmable through the lvds output driver management register (03h, table 14). by default, the output driver current is set to 3.5ma. the output driver current can be adjusted from 0.5ma to 7.5ma in 0.5ma steps (table 15). figure 6. detailed two-conversion timing diagram figure 7. serial-output detailed timing diagram n d5 d6 d7 d8 d9 d10 d11 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d0 d1 d2 d3 d4 d5 d6 d7 output data for sample n- 9 o utput data for sample n- 8 o utput data for sample n- 7 (v in _ + - v in_- ) (v clkin+ - v clkin- ) (v frame+ - v frame- ) (v clkout+ - v clkout - ) (v out_ + - v out_- ) n+1 n+1 t sample t sf t df (v frame+ - v frame- ) (v clkout+ - v clkout - ) (v out_ + - v out_- ) t cf t ch t od t od t cl d0 d1 d2 d3
ultra-low-power, octal, 12-bit, 50msps, 1.8v adc with serial lvds outputs MAX19527 18 the lvds output drivers also feature optional internal termination that can be enabled and adjusted by the lvds output driver management register (03h, table 14). by default, the internal output driver termination is disabled. see table 16 for all possible configurations. output driver level tests the lvds outputs (data, clock, and frame) can be configured to static logic-level test states through the lvds output driver level register (02h, table 9). the complete list of settings for the static logic-level test states can be found in tables 10, 11, and 12. data output test patterns the lvds data outputs can be configured to output several different, recognizable test patterns. test patterns are enabled and selected using the output data format and test pattern register (01h, table 5). a complete list of test pattern options is listed in table 7, and custom test pattern details can be found in the custom test pattern registers (07h, 08h, 09h) section (including tables 21, 22, and 23). power management the shdn input is used to toggle between two power- management states. power state 0 corresponds to shdn = 0, while power state 1 corresponds to shdn = 1. the pll sampling rate and power management register (00h) and the channel power management registers (05h and 06h) fully define each power-management state. by default, shdn = 1 shuts down the device and shdn = 0 returns the adcs to full-power operation. use of the shdn input is not required for power management. for either state of shdn, complete power-manage - ment flexibility is provided, including individual adc channel power-management control, as well as the option of which reduced power-mode to utilize in each power state. the available reduced-power modes are called sleep mode and nap mode. the device cannot enter either of these states unless no adc channels are active in the current power state (table 4). in nap mode, the reference, duty-cycle equalizer, and clock-multiplier pll circuits remain active for rapid wake-up time. in nap mode, the externally applied clock signal must remain active for the duty-cycle equalizer and pll to remain locked. typical wake-up time from nap mode is 2 f s. in sleep mode, all circuits are turned off except for the bandgap voltage-generation circuit. all registers retain previously programmed values during sleep mode. typical wake-up time from sleep mode is 10ms, which is dominated by the rc time constants on refio and refh/refl. power on and reset the user-programmable register default settings and other factory-programmed settings are stored in a non - volatile memory. upon device power-up, these values are loaded into the control registers. the operation occurs after the application of a valid supply voltage to avdd and ovdd, and the presence of an input clock signal. the user-programmed register values are retained as long as the avdd and ovdd voltages are applied. a reset condition overwrites all user-programmed registers with the default factory values. the reset condition occurs on power-up and can be initiated while powered with a software write command (write 5ah) through the serial-port interface to the special function register (10h). the reset time is proportional to the adc clock period and requires 415 f s at 50msps. 3-wire serial peripheral interface (spi) the adc operates as a slave device that sends and receives data through a 3-wire spi interface. a master device must initiate all data transfers to and from the device. the device uses an active-low spi chip- select input ( cs ) to enable communication with timing controlled through the externally generated spl clock input (sclk). all data is sent and received through the bidirectional spi data line (sdio). the device has 10 user-programmable control registers and one special- function register, which are accessed and programmed through this interface. spi communication format figure 8 shows an adc spi communication cycle. all spi communication cycles are made up of two bytes of data on sdio and require 16 clock cycles on sclk to be completed. to initiate an spi read or write communication cycle, cs must first transition from a logic-high to a logic-low state. while cs remains low, serial data is clocked in from sdio on rising edges of sclk and clocked out (for a read) on the falling edges of sclk. when cs is high, the device does not respond to sclk transitions, and no data is read from or written to sdio. cs must transition back to logic-high after each read/write cycle is completed.
ultra-low-power, octal, 12-bit, 50msps, 1.8v adc with serial lvds outputs MAX19527 19 the first byte transmitted on sdio is always provided by the master. the adc (slave device) clocks in the data from sdio on each rising edge of sclk. the first bit received selects whether the communication cycle is a read or write. logic 1 selects a read cycle, while logic 0 selects a write cycle. the next 7 bits (msb first) are the register address for the read or write cycle. the address can indicate any of the 10 user-programmable control registers (00h to 09h), or the special-function register (10h, write only). attempting to read/write with any other address has no effect (table 1). the second byte on sdio is sent to the adc in the case of a write, or received from the adc in the case of a read. for a write command, the device continues to clock in the data on sdio on each rising edge of sclk. in the case of a read command, the device writes data to sdio on each falling edge of sclk. the data byte is transmitted and received msb first in both cases. the detailed spi timing requirements are shown in figure 9. user-programmable control registers the adc has 10 user-programmable control regis - ters, and one special-function register (table 1). each register is set to its power-on-reset (por) default value when the device powers up or after a reset condition clears. pll sampling rate and power management register (00h) the pll sampling rate and power-management register (00h, table 2) has two distinct functions. the first is to adjust the internal pll to facilitate a wide range of input sampling frequencies. the second is to set the type of power-down mode used by each power state (set by shdn). figure 8. spi communication cycle figure 9. spi timing diagram sdio sclk addres s data (write or read ) 0 = writ e 1 = read cs r/w a6 a5 a4 a3 a2 a1 d7 d6 d5 d1 a0 d4 d3 d2 d0 t cs s cs sclk sdio t cs h t sclk t sds t sdh t sdd
ultra-low-power, octal, 12-bit, 50msps, 1.8v adc with serial lvds outputs MAX19527 20 the pll[2:0] bits (00h[6:4]) are used to program the clock multiplier for the internal pll in order to set the input sampling frequency range. the default setting is pll[2:0] = 001, which allows for 39mhz to 50mhz operation. see table 3 for the full range of pll settings and the corresponding sampling frequencies. the nap_shdn1 (00h[1]) and nap_shdn0 (00h[0]) bits are used to set the state of the adc when all channels are turned off for the shdn = 1 and shdn = 0 power- management states, respectively. when they are set to logic 0, the device enters sleep mode if no channels are enabled in that power state. when they are set to logic 1, the device instead enters nap mode if no channels are enabled for that power state. if even one channel is active in the current power state, the device cannot enter nap or sleep mode (table 4). the default states are nap_shdn1 = 0 and nap_shdn0 = 1, meaning that if all channels are disabled in the corresponding power state, shdn = 1 corresponds to sleep mode and shdn = 0 corresponds to nap mode. output data format and test pattern register (01h) the output data format and test pattern register (01h, table 5) has several functions. the first is used to adjust the lvds output bit order and data format. the second is used to set the clkout phase with respect to the output frame. finally, this register is used to enable and select test pattern outputs. table 1. summary of user-programmable control registers table 3. pll frequency control settings (00h[6:4]) table 2. pll sampling rate and power management (00h) x = dont care. address read/write por state function 00h r/w 0001-0001 pll sampling rate and power management 01h r/w 0000-0000 output data format and test patterns 02h r/w 0000-0000 lvds output driver level 03h r/w 0000-0000 lvds output driver management 04h r/w 0000-1000 input common mode and clkin control 05h r/w 1111-1111 channel power management: shdn0 06h r/w 0000-0000 channel power management: shdn1 07h r/w 1010-1010 custom test patterns 1 08h r/w 0101-0101 custom test patterns 2 09h r/w 0101-1010 custom test patterns 3 0ah to 0fh reserved reserved registers (do not use) 10h r/w special function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pll[2:0] nap_shdn1 nap_shdn0 clock multiplier setting minimum sampling frequency (mhz) maximum sampling frequency (mhz) pll[2] pll[1] pll[0] 0 0 0 not used 0 0 1 39 50 0 1 0 28.5 39 0 1 1 25 28.5 1 x x not used
ultra-low-power, octal, 12-bit, 50msps, 1.8v adc with serial lvds outputs MAX19527 21 the lvds data output format can be adjusted using the data_format bit (01h[1]) and the bit_order bit (01h[0]). the default state for both is logic 0, correspond - ing to a binary digital output code, presented lsb first. setting bit_order to logic 1 changes the lvds output data to an msb-first format. setting data_format to logic 1 changes the lvds output format from binary to twos complement. table 6 contains the lvds output data format programming details. the phase of the serial lvds output clock (clkout) can be adjusted, relative to the output data frame, by using the clkout_phase[1:0] bits (01h[3:2]). the default state for clkout_phase[1:0] is 00, and by changing this value the default phase relationship can be adjusted in 90 n increments. figure 10 illustrates both the default phase relationship (between an output data frame and the output clock), as well as the other three settings (shown with the default lsb first output data format). the serial lvds outputs also feature programmable test patterns for data timing alignment. by default, the test_data bit (01h[4]) is set to logic 0, enabling normal channel data outputs. by setting test_data to logic 1, test data output patterns are enabled. the adc has five preset test data output settings, as well as one custom pattern setting (custom test patterns are programmed through registers 07h, 08h, and 09h). the test_pattern[2:0] bits (01h[7:5]) are used to select the type of output test pattern. all test patterns consist of a sequence of one or more 12-bit data frames. table 7 contains the test pattern programming details. pseudo-random data patterns are bit sequences with - out regard to bit position within the frame. the short sequence repeats every 2 9 - 1 (511) bits. the bit sequence is generated according to the itu-t 0.150 standard, with an initial value shown in table 8. the long sequence repeats every 2 23 - 1 (8,388,607) bits accord - ing to itu-t 0.150 with an initial value shown in table 8 and an inverted bit stream. table 4. power-management programming table table 5. output data format and test pattern (01h) table 6. lvds output data format programming x = dont care. shdn nap_shdn0 00h[0] chx_shdn0 05h[7:0] nap_shdn1 00h[1] chx_shdn1 06h[7:0] MAX19527 state 0 0 0000-0000 x xxxx-xxxx sleep mode 0 1 0000-0000 x xxxx-xxxx nap mode 0 x one or more bits set to 1 x xxxx-xxxx active mode 1 x xxxx-xxxx 0 0000-0000 sleep mode 1 x xxxx-xxxx 1 0000-0000 nap mode 1 x xxxx-xxxx x one or more bits set to 1 active mode bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 test_pattern[2:0] test_data clkout_phase[1:0] data_format bit_order data_format bit_order lvds output data format 0 0 binary, lsb first (default) 0 1 binary, msb first 1 0 twos complement, lsb first 1 1 twos complement, msb first
ultra-low-power, octal, 12-bit, 50msps, 1.8v adc with serial lvds outputs MAX19527 22 lvds output driver level register (02h) use the lvds output driver level register (02h, table 9) to test the lvds output driver static logic levels (out_, clkout_, frame_) and to set the output common- mode voltage for all lvds outputs. to test the lvds outputs at static logic levels, the test_frame_level[1:0], test_clkout_level[1:0], and test_data_level[1:0] bits (02h[5:0]) are used. the lsb of each, when set to logic 0 (default), disables the static output level test (normal data output). when the lsb of each is set to logic 1, the static output level test is enabled. the msb of each is then used to determine if the static output is logic 1 or 0 (matches the logic state of the msb). for detailed programming information, see tables 10, 11, and 12. to set the lvds output common-mode voltage, use the lvds_cm[1:0] bits (02h[7:6]). by default, lvds_cm[1:0] is set to 00, which corresponds to a default setting of 1.2v for the lvds output common-mode voltage. table 13 contains complete programming details. figure 10. serial lvds output clock (clkout) phase adjustment table 7. test pattern programming x = dont care. v fram e v clkout v out_ d0 d1 d2 d3 clkout_phase[1:0] = 00 (default) v fram e v clkout v out_ d0 d1 d2 d3 clkout_phase[1:0] = 01 v fram e v clkout v out_ d0 d1 d2 d3 clkout_phase[1:0] = 10 v fram e v clkout v out_ d0 d1 d2 d3 clkout_phase[1:0] = 11 v fram e = (v frame+ - v frame- ) v clkout = (v clkout + - v clkout - ) v out_ = (v out_ + - v out_ -) test_data test_pattern[2:0] test pattern format 0 x x x disabled, normal data output (default) 1 0 0 0 data skew (010101010101), repeats every frame 1 0 0 1 data sync (111111000000), repeats every frame 1 0 1 0 custom test pattern, repeats every two frames 1 0 1 1 ramping pattern from 0 to 4095 (repeats) 1 1 0 0 pseudo-random data pattern, short sequence (2 9 ) 1 1 0 1 pseudo-random data pattern, long sequence (2 23 ) 1 1 1 0 not used 1 1 1 1 not used
ultra-low-power, octal, 12-bit, 50msps, 1.8v adc with serial lvds outputs MAX19527 23 lvds output driver management register (03h) use the lvds output driver management register (03h, table 14) to set the lvds output drive current and to enable and set the value of the internal lvds output termination. the lvds output drive current is fully configurable through the lvds_iadj[3:0] bits (03h[3:0]). the default setting for lvds_iadj[3:0] is 0000, which corresponds to a 3.5ma output drive current (350mv at 100 i ). the output drive current can be reprogrammed from 0.5ma to 7.5ma in 0.5ma increments. table 15 contains complete programming details. the lvds output driver features optional internal termina - tion that is programmable through the lvds_term[2:0] bits (03h[6:4]). by default, lvds_term[2:0] is set to 000, disabling the optional internal termination. table 16 contains the configuration details. input common-mode and clkin control register (04h) use the input common-mode and clkin control register (04h, table 17) to enable a self-biased, input common-mode voltage level, and to enable optional internal termination between the differential clkin_ inputs. table 8. pseudo-random data pattern table 9. lvds output driver level (02h) table 10. test data (out_) level programming table 11. test clkout level programming table 12. test frame level programming x = dont care. x = dont care. x = dont care. sequence initial value first three samples short (2 9 ) 0x0df 0xdf9, 0x353, 0x301 long (2 23 ) 0x29b80a 0x591, 0xfd7, 0x0a3 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 lvds_cm[1:0] test_frame_level[1:0] test_clkout_level[1:0] test_data_level[1:0] test_data_level[1:0] data (out_) output x 0 normal data output 0 1 output low (static) 1 1 output high (static) test_clkout_level[1:0] clkout output x 0 normal clkout output 0 1 output low (static) 1 1 output high (static) test_frame_level[1:0] frame output x 0 normal frame output 0 1 output low (static) 1 1 output high (static)
ultra-low-power, octal, 12-bit, 50msps, 1.8v adc with serial lvds outputs MAX19527 24 the cmi_self bit (04h[0]) is used to enable the optional, self-biased input common-mode voltage. by default, cmi_self is set to logic 0, disabling this feature. setting cmi_self to logic 1 allows the specified common-mode voltage to be applied to the analog input pins through approximately 2k i resistance. the level of the input common-mode voltage is set by the cmi_adj[2:0] bits (04h[3:1]). the default setting for cmi_adj[2:0] is 100, which corresponds to a cmout voltage of 1100mv. the internally supplied and programmed input common- mode voltage is always available on the cmout pin. table 18 contains configuration options, and figure 2 details the input configuration. by default, the clkin_term bit (04h[4]) is set to logic 0, disabling the internal, differential clkin input termination resistance. to enable the optional internal differential 100 i termination resistance (from clkin+ to clkin-), set clkin_term to logic 1 (figure 4). channel power management: shdn0 (05h) and shdn1 (06h) registers the shdn input allows the adc to support two individually programmed power states. the channel power management (cpm): shdn0 register (05h) is used to individually enable or disable each channel for power state 0 (shdn = 0). the default state of table 13. lvds output common-mode voltage adjustment table 14. lvds output driver management (03h) table 15. lvds output drive current configuration table 16. lvds output drive internal termination configuration lvds_cm[1:0] lvds output common-mode voltage (v) 0 0 1.2 (default) 0 1 1.0 1 0 0.8 1 1 0.6 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 lvds_term[2:0] lvds_iadj[3:0] lvds_iadj[3:0] drive current (ma) 0 0 0 0 3.5 (default) 0 0 0 1 0.5 0 0 1 0 1.0 0 0 1 1 1.5 0 1 0 0 2.0 0 1 0 1 2.5 0 1 1 0 3.0 0 1 1 1 3.5 1 0 0 0 4.0 1 0 0 1 4.5 1 0 1 0 5.0 1 0 1 1 5.5 1 1 0 0 6.0 1 1 0 1 6.5 1 1 1 0 7.0 1 1 1 1 7.5 lvds_term[2:0] lvds internal termination ( i ) 0 0 0 disabled (default) 0 0 1 800 0 1 0 400 0 1 1 267 1 0 0 200 1 0 1 160 1 1 0 133 1 1 1 100
ultra-low-power, octal, 12-bit, 50msps, 1.8v adc with serial lvds outputs MAX19527 25 cpm: shdn0 is 1111-1111, which causes power state 0 to enable all eight channels (by default). the cpm: shdn1 register (06h) is used to enable or disable each channel for power state 1 (shdn = 1). the default state of cpm: shdn1 is 0000-0000, which causes power state 1 to disable all eight channels (by default). both power states are independently configurable for any combination of enabled and disabled channels (tables 19 and 20). custom test pattern registers (07h, 08h, 09h) the custom test pattern (1, 2, and 3) registers are used to create a user-programmed test pattern sequence (test_ data = 1, test_pattern[2:0] = 010, see tables 5 and 7). the data for the custom test pattern sequence is divided among the three custom test pattern registers (tables 21, 22, and 23). the custom test pattern comprises a series of two, 12-bit sequences (bits_custom1[11:0] first, followed by bits_custom2[11:0]) that repeat continu - ously. table 17. input common mode and clkin control (04h) table 18. input common-mode voltage configuration table 19. channel power management: shdn0 (05h) table 20. channel power management: shdn1 (06h) table 21. custom test pattern 1 (07h) table 22. custom test pattern 2 (08h) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 clkin_term cmi_adj[2:0] cmi_self cmi_adj[2:0] input common-mode voltage (mv) 0 0 0 1020 0 0 1 1040 0 1 0 1060 0 1 1 1080 1 0 0 1100 (default) 1 0 1 1120 1 1 0 1140 1 1 1 1160 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ch8_shdn0 ch7_shdn0 ch6_shdn0 ch5_shdn0 ch4_shdn0 ch3_shdn0 ch2_shdn0 ch1_shdn0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ch8_shdn1 ch7_shdn1 ch6_shdn1 ch5_shdn1 ch4_shdn1 ch3_shdn1 ch2_shdn1 ch1_shdn1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bits_custom1[7:0] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bits_custom2[7:0]
ultra-low-power, octal, 12-bit, 50msps, 1.8v adc with serial lvds outputs MAX19527 26 reserved registers (0ah to 0fh) these registers are reserved and should not be used or programmed. it is possible to read from or write to these registers, but the commands have no effect on device operation. special function register (10h) the special function register has two key functions: soft - ware device reset and device status. to initiate a soft - ware device reset, write the command 5ah to the special function register. do not write any other values to this register as they could permanently alter the device con - figuration. when read, the register returns a status byte with the information described in table 24. applications information analog inputs the adc provides better sfdr and thd with fully differential input signals than a single-ended input drive. in differential input mode, even-order harmonics are lower as both inputs are balanced, and each of the adc inputs only require half the signal swing compared to single-ended input mode. single-ended operation for the device is not recommended. ac-coupled inputs an rf transformer provides an excellent solution for converting a single-ended signal to a fully differential signal (figure 11). cmout provides the common-mode voltage for an ac-coupled input. the transformer shown has an impedance ratio of 1:1. alternatively, a different step-up transformer can be selected to reduce the drive requirements. a reduced signal swing from the input driver can also improve the overall distortion. clock inputs differential, ac-coupled clock inputs for optimum dynamic performance, the clock inputs to the device should be driven with an ac-coupled differential signal. however, frequently the available clock source is single-ended. figure 12 demonstrates one method for converting a single-ended clock sig - nal into a differential signal with a transformer. in this example, a coilcraft transformer (ttwb-2-b), whose impedance ratio from primary to secondary is 1:2. the signal in this example is terminated into a series combination of two 50 resistors with their common node ac-coupled to ground. figure 12 illustrates the second - ary side of the transformer to be coupled directly to the clock inputs. since the clock inputs are self-biasing, the center tap of the transformer must be ac-coupled to ground or left unconnected. if the center tap of the transformers secondary side is dc-coupled to ground, it is necessary to add blocking capacitors in series with the clock inputs. clock jitter performance can be enhanced if the clock signal has a high slew rate at the time of its zero- crossing. therefore, if a sinusoidal source is used to drive the clock inputs, the clock amplitude should be as large as possible to maximize the zero-crossing slew rate. the back-to-back schottky diodes shown in figure 12 are not required as long as the input signal is held to a differential voltage potential of 3v p-p or less. if a larger amplitude signal is provided (to maximize the zero-crossing slew rate), then the diodes serve to limit the differential signal swing at the clock inputs. any differential mode noise coupled to the clock inputs translates to clock jitter and degrades the snr perfor - mance of the device. any differential mode coupling of the analog input signal into the clock inputs results in harmonic distortion. consequently, it is important that the clock lines be well isolated from the analog signal input and from the digital outputs. table 23. custom test pattern 3 (09h) table 24. special function register (10h) status byte (read) status bit no. read value description 7 0 reserved 6 0 reserved 5 0 or 1 1 = rom read in progress 4 0 or 1 1 = rom read completed, and register data is valid (checksum ok) 3 0 reserved 2 1 reserved 1 0 or 1 reserved 0 0 or 1 1 = duty-cycle equalizer dll is locked bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bits_custom2[11:8] bits_custom1[11:8]
ultra-low-power, octal, 12-bit, 50msps, 1.8v adc with serial lvds outputs MAX19527 27 figure 11. transformer-coupled input drive figure 12. single-ended-to-differential clock input figure 13. single-ended clock input with duty-cycle adjustment singe-ended, ac-coupled clock inputs in single-ended operation, the clock signal is applied to the devices positive clock input (clk+) through a buffer amplifier (fairchild nc7wv04p6x). the negative input (clk-) is connected to ground in this mode. in single- ended clock configuration, an external 10k potentiometer can be utilized to control the duty cycle of the clock input signal. measure the clock input to the device after the buffer and adjust the potentiometer until the desired duty cycle is achieved. the circuit in figure 13 allows for duty- cycle adjustments between 20% and 80%. 39pf 10i cmout in_- in_+ 100i 100i 100i 100i 10i 1 f 39pf MAX19527 0.1f 0.1f analog input mini-circuit s (1:1) adt1-1wt+ n.c. clkin- clkin+ MAX19527 0.1f 0.01f 0.01f clock input coilcraft (1:2) ttwb-2-b n.c. n.c. 49.9i 49.9i centra l semiconductor cmpd6263s + avdd 100i 0.1f 10ki 49.9i 0.1f 100i clock input avdd clkin+ clkin- 100ki potentiometer: duty-cycle adjustment MAX19527 tinylogic ulp-a inverter, fairchild nc7wv04p6x
ultra-low-power, octal, 12-bit, 50msps, 1.8v adc with serial lvds outputs MAX19527 28 grounding, bypassing, and board layout the adc requires high-speed board layout design tech - niques to achieve optimal dynamic performance. refer to the MAX19527 ev kit data sheet for a board layout reference. locate all bypass capacitors as close as possible to the device, preferably on the same side as the adc, using surface-mount components for minimum inductance. bypass the avdd and ovdd inputs with a separate 0.1 f f ceramic capacitor to gnd at both sides of the device (row a and row m). bypass cmout with a 1 f f ceramic capacitor to gnd. to use the internal reference, bypass refio with a 0.1 f f ceramic capacitor to gnd. for optimal performance using either an internal or external reference, bypass refh to rehl with a 0.1 f f ceramic capacitor. multilayer boards with ample ground and power planes produce the highest level of signal integrity. isolate the ground plane from any noisy digital system ground planes. route high-speed digital signal traces away from sensitive analog traces. keep all signal lines short and free of 90 n turns. ensure that the differential analog input network layout is symmetric and that all parasitics are balanced equally. ensure that the lvds outputs are routed as matched length, 100 i terminated, differential transmission lines. refer to the MAX19527 ev kit data sheet for an example of symmetric input layout. parameter definitions integral nonlinearity (inl) inl is the deviation of the measured transfer function from a best-fit straight line. worst-case deviation is defined as inl. differential nonlinearity (dnl) dnl is the difference between the measured transfer - function step width and the ideal value of 1 lsb. a dnl error specification of less than 1 lsb guarantees no missing codes and a monotonic transfer function. dnl deviations are measured at each step of the transfer function and the worst-case deviation is defined as dnl. offset error offset error is a parameter that indicates how well the actual transfer function matches the ideal transfer function at midscale. ideally, the midscale transition occurs at 0.5 lsb above midscale. the offset error is the amount of deviation between the measured midscale transition point and the ideal midscale transition point. gain error gain error is a figure of merit that indicates how well the slope of the measured transfer function matches the slope of the ideal transfer function based on the specified full-scale input voltage range. the gain error is defined as the relative error of the measured transfer function and is expressed as a percentage. small-signal noise floor (ssnf) ssnf is the integrated noise and distortion power in the nyquist band for small-signal inputs. the dc offset is excluded from this noise calculation. for this converter, a small signal is defined as a single tone with an amplitude less than -35dbfs. this parameter captures the thermal and quantization noise characteristics of the converter and can be used to help calculate the overall noise figure of a receive channel. near-carrier signal-to-noise ratio (ncsnr) near-carrier snr is defined as the ratio of the power in a near full-scale sinusoidal signal to the noise power measured at 1khz offset from the signal. the noise power is normalized to 1hz bandwidth. the near-carrier noise measured in a single adc channel can be corre - lated to the near-carrier noise in other channels in a mul - tichannel adc. if that is the case, if output signals from multiple channels are summed, the addition process does not provide full processing gain of 10 x log(n), where n is the number of channels. near-carrier snr for an 8-channel coherent sum is defined for the case of apply - ing an in-phase sinusoidal signal to all 8 adc channels, and computing the near-carrier snr for the digital sum of all eight outputs. signal-to-noise ratio (snr) for a waveform perfectly reconstructed from digi - tal samples, the theoretical maximum snr is the ratio of the full-scale analog input (rms value) to the rms quantization error (residual error). the ideal, theoretical mini - mum analog-to-digital noise is caused by quantization error only and results directly from the adcs resolution (n bits): snr db[max] = 6.02 db x n + 1.76 db in reality, there are other noise sources besides quantiza - tion noise (e.g., thermal noise, reference noise, clock jitter, etc.). snr is computed by taking the ratio of the rms signal to the rms noise. rms noise includes all spectral compo - nents to the nyquist frequency excluding the fundamental, the first six harmonics (hd2Chd7), and the dc offset. rms rms signal snr 20 log noise ? ? = ? ? ? ?
ultra-low-power, octal, 12-bit, 50msps, 1.8v adc with serial lvds outputs MAX19527 29 signal-to-noise and distortion (sinad) sinad is computed by taking the ratio of the rms signal to the rms noise plus the rms distortion. rms noise includes all spectral components to the nyquist frequency excluding the fundamental, the first six harmonics (hd2Chd7), and the dc offset. rms distortion includes the first six harmonics (hd2Chd7). rms 2 2 rms rms signal snr 20 log noise distortion ? ? ? ? = ? ? ? ? + ? ? single-tone spurious-free dynamic range (sfdr) sfdr is the ratio expressed in decibels of the rms amplitude of the fundamental (maximum signal component) to the rms amplitude of the next largest spurious component, excluding dc offset. total harmonic distortion (thd) thd is the ratio of the rms of the first six harmon - ics of the input signal to the fundamental itself. this is expressed as: 2 2 2 2 2 2 2 3 4 5 6 7 1 v v v v v v thd 20 log v ? ? + + + + + ? ? = ? ? ? ? ? ? v 1 is the fundamental amplitude and v 2 Cv 7 are the amplitudes of the 2nd-order through 7th-order harmon - ics (hd2Chd7). intermodulation distortion (imd) imd is the ratio of the rms sum of the intermodulation products to the rms sum of the two fundamental input tones. this is expressed as: 2 2 2 2 im1 im2 im13 im14 2 2 1 2 v v v v imd 20 log v v ? ? + + + + ? ? = ? ? ? ? + ? ? ?? v 1 and v 2 are amplitudes of the two fundamental inputs, and v imn is the amplitude of the nth intermodulation product. the fundamental input tone amplitudes (v 1 and v 2 ) are at -6.5dbfs. fourteen intermodulation products (v imn ) are used in the adc imd calculation. the inter - modulation products are the amplitudes of the output spectrum at the following frequencies, where f in1 and f in2 are the fundamental input tone frequencies: u second-order intermodulation products: f in1 + f in2 , f in2 - f in1 u third-order intermodulation products: 2 x f in1 - f in2 , 2 x f in2 - f in1 , 2 x f in1 + f in2 , 2 x f in2 + f in1 u fourth-order intermodulation products: 3 x f in1 - f in2 , 3 x f in2 - f in1 , 3 x f in1 + f in2 , 3 x f in2 + f in1 u fifth-order intermodulation products: 3 x f in1 - 2 x f in2 , 3 x f in2 - 2 x f in1 , 3 x f in1 + 2 x f in2 , 3 x f in2 + 2 x f in1 overdrive recovery time overdrive recovery time is the time required for the adc to recover from an input transient that exceeds the full-scale limits. the specified overdrive recovery time is measured with an input carrier that exceeds the full- scale limits by 6dbfs. package information for the latest package outline information and land pat - terns, go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suf - fix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. 144 ctbga x14400-3 21-0492
ultra-low-power, octal, 12-bit, 50msps, 1.8v adc with serial lvds outputs MAX19527 maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 30 maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2010 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 6/10 initial release

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